• Timer1 ISR: In the first three Timer1 overflow ISRs, the corresponding Odd PWM output is turned off in each ISR. The complementary output is turned on after a dead time of five cycles (1 ms). In the fourth Timer1 overflow ISR, the PWM cycle is restarted. All PWMs are turned OFF and the timer is loaded with the value corresponding to the lowest duty cycle value. This is repeated for each PWM cycle.
• Timer0 ISR: A flag is set to indicate that the Sine output should advance by 10 degrees on the Sine table. The Timer0 registers are reloaded with the value corresponding to the motor frequency reference.
• INT ISR: The INT pin is used to interface hardware overcurrent fault. Motor current is compared with a fixed voltage reference using an op amp comparator. Each time the motor current exceeds the reference, in INT ISR a count (0C_COUNT) is decremented. If the count reaches zero in one Timer0 cycle, then the motor is stopped and overcurrent is indicated. This count is reset in every Timer0 ISR.
• Timer0 ISR: A flag is set to indicate that the Sine output should advance by 10 degrees on the Sine table. The Timer0 registers are reloaded with the value corresponding to the motor frequency reference.
• INT ISR: The INT pin is used to interface hardware overcurrent fault. Motor current is compared with a fixed voltage reference using an op amp comparator. Each time the motor current exceeds the reference, in INT ISR a count (0C_COUNT) is decremented. If the count reaches zero in one Timer0 cycle, then the motor is stopped and overcurrent is indicated. This count is reset in every Timer0 ISR.
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